Update

I have been doing some research on the PDP-14 and would like to get any information that I can on this controller. Everything that I know exists is on bitsavers, which is very little. I have written a PDP-14 simulator for SIMH that can communicate with a PDP-8 SIMH simulator. The simulator passes all the MAINDEC-14 tests that I have.

What I really need is information on how the MM14-E operated, specifically what instruction was used to write to program memory. My guess is that it was a modification of TRM instruction with the PAUSE state modified so that it transfered the INPUT register to the MB register and then to the memory address determined by PC1.

History

I acquired pieces of a PDP-14 along with the PDP-8. They had been used together as a machine controller for a prototype computer controlled punch press. The PDP-8 and -14 replaced a completely hardwired digital sequencer that was used to control a punch press for exhibit at the International Machine Tool Show (IMTS) in 1970.

After experience with the harwired logic control, it was recognized that a more flexible control was necessary and so a PDP-8 and a PDP-14 along with some I/O were acquired and the machine retrofitted with the computer. A paper tape or operator commands at a teletype terminal could completely reconfigure the machine, including installing new toolings. Unfortunately, the stamping industry at the time was not ready for such automation. At about 90% of completion, the project was cancelled and the machine was parted out. The PDP-8 was kept, and some of the PDP-14 modules were retained. Critical PDP-14 components were discarded, including the mainframe assembly and backplane. Fortunately, all the hardware documentation was retained.

I also have copies of the PDP-8 control program used. The PDP-14 was a single bit computer which executed instructions supplied by a braided core ROM. This memory consisted of a matrix of wires and current sensing cores. A pulse of current through a wire was sensed by a transformer core, and the resulting pattern of excited cores was used to determine the contents of a memory location. This is identical to the rope core ROM control store of the Apollo Guidance Computer (AGC) used to get to the moon. Interestingly, there is now a simulator for the AGC complete with a version of software for the CM and the LM.

This PDP-14 never had a braided ROM. The design allowed a PDP-8 to supply the PDP-14 with instructions to be executed. This was how the -14 was used. Because there was no PDP-14 program, the PDP-14 was essentially the industrial I/O interface for the PDP-8.

Hardware Architecture

The PDP-14 consisted of a control unit and several external boxes. The control unit included a variable sized ROM, which could be up to 4k of 12-bit instructions. Control memory was divided into 256 word pages. There were 16 pages in the maximum control memory space. There were 4 external box types: I-box, O-box, A-box and S-box.

The I-boxes (BX14) supplied discrete inputs from the controlled system. Up to 256 inputs could be addressed.

The O-boxes (BY14) controlled up to 255 actuators in the controlled system.

The A-boxes could be filled with timer modules to control time driven events or retentive storage modules which were not cleared with power loss. A-boxes occupied the output address space along with the O-boxes.

The S-boxes were essentially the same as the O-boxes, except that there was no real output device. It provided a means of storing intermediate results. S-boxes also occupied the output address space.

Registers

Most information about the PDP-14 on the internet is a quick note that it was a controller with only 1 bit. It was actually more sophisticated than that.

The PDP-14 has 2 flags visible to the programmer: TEST and EXT MODE. TEST holds the result of the last TYF or TXF instruction and program flow can be controlled by conditional jump instructions that examine the bit. EXT MODE flag causes the controller to stop executing instructions from memory and wait for instructions to be supplied by an external computer.

The PDP-14 has 7 12 bit registers: IR, PC1, PC2, MB, SPARE, INPUT and OUTPUT. The TRR instructions can move data between each of these registers with a few exceptions. PC1 and SPARE have increment and decrement capabilites and so the TRR can also be encoded so that it will modify the value that is loaded into the reigster. A JMR instruction is actually a specific TRR in which PC2 is transfered to PC1. A SKP is a TRR in which PC1 is loaded with PC1 + 1.

Options

• DA14-A - Parallel computer interface to connect to a PDP-8/e, PDP-8/I, PDP-8/L or PDP-12
• DL14-A,B,C,D,E,F - Serial computer interface
• MAP14 - Communications system between a PDP-8/e and multiple PDP-14 controllers. There is very little detail available on this and so it is not clear how it was used. One thought is that is was used as distributed I/O for the PDP-8.
• MM14-E - Writable program memory. This used an MM11-E 4k or 8k word UNIBus memory module to provide the PDP-14 with writable program memory. Information on the option is very limited. The memory could only be written when the controller was in External Mode, so the memory could only be used for control program storage. The PDP-14 itself had no way to write to the memory.

Programming Software

Programming for the PDP-14 was done on a PDP-8 computer. Several different programs were used to perform different functions.

• BOOL-14 - This program converted boolean equations into PDP-14 machine instructions. It would seem from the documentation that expressions were converted to a two level Product-of-Sums form and then the sums were done by sequences of TXN, TYN, TXF and TYF instructions and the products were done by JFN or JFF instructions.
• PAL-14 - This program assembled PDP-14 assembly language into machine instructions.
• SIM-14 - This program allowed a PDP-8 to simulate a PDP-14.

I do not have paper tapes of these. I wish I did. They are to be run on a bare PDP8 without an OS.

Instruction Set

The table below is only a list of the instructions typically used to generate ladder logic. The complete list of instructions is much longer.

Instruction		Definition
Symbolic	Numeric
JFN NNN	5400 + NNN	Jump to location NNN if the TEST flag is now ON and execute the instructions beginning with the instruction in location NNN. (If the flag is OFF, the instructions following the JFN continue to be executed in sequence.) The Test flag is set OFF, regardless of its original state.
JFF NNN	5000 + NNN	Jump to location NNN if the TEST flag is now OFF and execute the instructions beginning with the instruction in location NNN. (If the flag is ON, the instructions following the JFN continue to be executed in sequence.) The Test flag is set OFF, regardless of its original state.
JMP NNNN	4224 NNNN	Jump to location NNNN unconditionally. Execution of the PDP-14 program preceeds sequentially beginning with the instruction in location NNNN. JMP is a two location instruction; the absolute address of the "jump-to" location is stored in the location following that which contains the JMP instruction.
SKP	0344	Skip the following memory location unconditionally. This instructon causes the PDP-14 to not execute the instruction which is stored in the next sequential location. Sequential execution continues with the instruction stored in the second location following the SKP instruction.
JMS NNNN	4645 NNNN	Jump to the subroutine beginning in location NNNN. The PDP-14 executes in sequence the instructions beginning with the instruction stored in location NNNN, and terminated by a JMR instruction. The JMS instruction is a two-location instruction which may directly address all PDP-14 memory.
JMR	0354	Jump return to the location following the second part of the JMS instruction. The JMR must always be paired with a JMS instruction.
TXN XXX	2400 + XXX	Test input XXX for the ON state. If input XXX is ON and the TEST flag is currently OFF, the TEST flas is set ON. Otherwise the flag remains unchanged.
TXF XXX	2000 + XXX	Test input XXX for the OFF state. If input XXX is off and the TEST flag is currently OFF, the TEST flag is set ON. Otherwise the flag remains unchanged.
TYN YYY	1400 + YYY	Test output YYY for the ON state. If output YYY is ON and the TEST flag is currently OFF, the TEST flag is set ON. Otherwise, the flag remains unchanged.
TYF YYY	1000 + YYY	Test output YYY for the OFF state. If output YYY is OFF and the TEST flag is currently OFF, the TEST flag is set ON. Otherwise the flag remains unchanged.
SYN YYY	3400 + YYY	Set output YYY to the ON state. Output YYY remains ON until it is set OFF by a SYF or CLR instruction.
SYF YYY	3000 + YYY	Set output YYY to the OFF state. Output YYY remains OFF until it is set ON by a SYN instruction.
CLR	3377	Set all PDP-14 outputs to the OFF state. This instruction sets every output OFF unconditionally (with the exception of the retentive memories) and it should not be used in normal conditions.
NNN = 8-bit relative page address NNNN = 12-bit absolute address XXX = 8-bit input address YYY = 8-bit output address

Next Generation

The PDP-14 was followed by the PDP-14/30 which had a similar, but not binary compatible instruction set. The PDP-14/30 used an OMINIBUS backplane, removing the wirewrapped backplane and improving reliability. Called the Industrial 14, it also introduced the VT14 programming terminal which was a PDP-8/e in a VT52 housing with a raster video display and an application specific keyboard.